module top(
           input clk,
           input rst_n,
           input data_in,
           output reg data_out
       );

parameter s0 = 2'b00;
parameter s1 = 2'b01;
parameter s2 = 2'b10;

reg [1: 0] state, state_next;

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			state <= s0;
		else
			state <= state_next;
	end

always@( * )
	begin
		if (!rst_n)
			state_next = s0;
		else
			begin
				case (state)
					s0:
						state_next = data_in ? s1 : s0;
					s1:
						state_next = data_in ? s0 : s2;
					s2:
						state_next = data_in ? s2 : s1;
				endcase
			end
	end

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			data_out <= 0;
		else if (state == s1 && state_next == s0)
			data_out <= 1'b1;
	end
endmodule
